36) An assembly line has 3 fail safe sensors and one emergency shutdown switch. The line should keep moving unless any of the following conditions arise:
(i) If the emergency switch is pressed
(ii) If the sensor1 and sensor2 are activated at the same time.
(iii) If sensor 2 and sensor3 are activated at the same time.
(iv) If all the sensors are activated at the same time
Solution.
Suppose a combinational circuit for above case is to be implemented only with NAND Gates. How many minimum number of 2 input NAND gates are required?
No of 2-input NAND Gates required = 6 you can try the whole implementation.
37) What is the fundamental difference between a MOSFET and BJT ?
Solution.
In MOSFET,current flow is either due to electrons(n-channel MOS) or due to holes(p-channel MOS). In BJT, we see current due to both the carriers-electrons and holes. BJT is a current controlled device and MOSFET is a voltage controlled device.
38) What is the difference between a LATCH and a FLIP-FLOP? Write Verilog RTL code for each?
Solution.
Verilog Code :
39) Design a state machine to divide the clock by 5/2.
(Hint: 2 FSMs working on posedge and negedge)
Solution.
Step by Step Method to design any Clock Frequency Divider
Clock Frequency Division | Divider by a fractional number (Step by Step Approach)
Solution.
The threshold voltage of a MOSFET is affected by the voltage which is applied to the back contact. The voltage difference between the source and the bulk, VBS changes the width of the depletion layer and therefore also the voltage across the oxide due to the change of the charge in the depletion region. This results in a change in threshold voltage.
41) Why PMOS and NMOS are sized equally in a Transmission Gates?
Solution.
In Transmission Gate, PMOS and NMOS aid each other rather competing with each other. That's the reason why we need not size them like in CMOS. In CMOS design we have NMOS and PMOS competing which is the reason we try to size them proportional to their mobility.
42) What happens when the PMOS and NMOS are interchanged with one another in an inverter?
Solution.
If the source & drain also connected properly...it acts as a buffer. But suppose input is logic 1 O/P will be degraded 1. Similarly degraded 0; Hence, acts as a weak buffer.
43) Why is NAND gate preferred over NOR gate for fabrication?
Solution.
NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three times that of holes compared to NOR and thus the NAND is a faster gate.
Additionally, the gate-leakage in NAND structures is much lower. If you consider t_phl and t_plh delays you will find that it is more symmetric in case of NAND ( the delay profile), but for NOR, one delay is much higher than the other(obviously t_plh is higher since the higher resistance p mos's are in series connection which again increases the resistance).
44) Let A and B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay of the two series NMOS inputs A and B which one would you place near to the output?
Solution.
The late coming signals are to be placed closer to the output node i.e. A should go to the nmos that is closer to the output.
45) Design a 4:1 mux in Verilog.
Multiple styles of coding. e.g.
Using if-else statements
if(sel_1 == 0 && sel_0 == 0) output = I0;
else if(sel_1 == 0 && sel_0 == 1) output = I1;
else if(sel_1 == 1 && sel_0 == 0) output = I2;
else if(sel_1 == 1 && sel_0 == 1) output = I3;
Using case statement
case ({sel_1, sel_0})
00 : output = I0;
01 : output = I1;
10 : output = I2;
11 : output = I3;
default : output = I0;
endcase
What are the advantages / disadvantages of each coding style shown above?
How Synthesis tool will give result for above codes?
What happens if default statement is removed in case statement?
What happens if combination 11 and default statement is removed? (Hint Latch inference)
Solution.
https://www.vlsifacts.com/case-conditional-statements-synthesis-caution/
46) What is the difference between Behavior modeling and RTL modeling ?
Solution.
RTL : Register-Transfer-Level, an abstraction hardware functionality written with always blocks and assign statements that are synthesizable.
Behavioral : Mimics the desired functionality of the hardware but not necessarily synthesizable. There is no strict rules as long as the code generates the desired behavior. Guideline is to keep it simple and readable.
The key difference between RTL and Behavioral is the ability to synthesize. It is behavioral if you see # delay, wait statements, while loops, force/release statements, or hierarchical reference.
47) What is the difference between blocking assignments and non-blocking assignments ?
Solution.
Blocking assignment executes "in series" because a blocking assignment blocks execution of the next statement until it completes. Therefore the results of the next statement may depend on the first one being completed.
Non-blocking assignment executes in parallel because it describes assignments that all occur at the same time. The result of a statement on the 2nd line will not depend on the results of the statement on the 1st line.
<= Nonblocking Assignment
= Blocking Assignment
In Verilog, if you want to create sequential logic use a clocked always block with Nonblocking assignments. If you want to create combinational logic use an always block with Blocking assignments. Try not to mix the two in the same always block.
http://ftp.smart-dv.com/tidbits/blocking.html
48) Variable and signal which will be Updated first?
Solution.
Signals
49) What is meant by inferring latches, how to avoid it?
Solution.
Consider the following :
always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0})
2'd0 : out = i0;
2'd1 : out = i1;
2'd2 : out = i2;
endcase
In a case statement if all the possible combinations are not compared and default is also not specified like in example above a latch will be inferred, a latch is inferred because to reproduce the previous value when unknown branch is specified. For example in above case if {s1,s0}=3 , the previous stored value is reproduced for this storing a latch is inferred.
The same may be observed in IF statement in case an ELSE IF is not specified.
To avoid inferring latches make sure that all the cases are mentioned if not default condition is provided.
50) What is sensitivity list?
Solution.
The sensitivity list indicates that when a change occurs to any one of elements in the list change, begin…end statement inside that always block will get executed.
51) In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? if yes, why?
Solution.
Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk other wise it will result in pre and post synthesis mismatch.
52) Tell me the general structure of Verilog code you follow?
Solution.
A good template for your Verilog file is shown below.
// timescale directive tells the simulator the base units and precision of the simulation
`timescale 1 ns / 10 ps
module name (input and outputs);
// parameter declarations
parameter parameter_name = parameter value;
// Input output declarations
input in1; input in2; // single bit inputs
output [msb:lsb] out; // a bus output
// internal signal register type declaration - register types (only assigned within always statements).
reg register variable 1;
reg [msb:lsb] register variable 2;
// internal signal. net type declaration - (only assigned outside always statements) wire net variable 1;
// hierarchy - instantiating another module
reference name instance name ( .pin1 (net1), .pin2 (net2), . .pinn (netn) );
// synchronous procedures
always @ (posedge clock)
begin . end
// combinational procedures
always @ (signal1 or signal2 or signal3)
begin . end
assign net variable = combinational logic;
endmodule
53) Can you list out some of synthesizable and non synthesizable constructs?
Non Synthesizable :-
Initial, delays real, time, etc..
Synthesizable Constructs:-
assign, for loop, Gate Level Primitives, repeat with constant value.
54) Difference between Synchronous and Asynchronous reset? Write Verilog code for both ?
Verilog Code :
55) What do conditional assignments get inferred into?
Solution.
Conditionals in a continuous assignment are specified through the “? :” operator. Conditionals get inferred into a multiplexer.
For example, the following is the code for a simple multiplexer
assign wire1 = (sel==1'b1) ? a : b;
56) What logic is inferred when there are multiple assign statements targeting the same wire?
Solution.
It is illegal to specify multiple assign statements to the same wire in a synthesizable code that will become an output port of the module. The synthesis tools give a syntax error that a net is being driven by more than one source.
However, it is legal to drive a three-state wire by multiple assign statements.
57) What value is inferred when multiple procedural assignments made to the same reg variable in an always block?
Solution.
When there are multiple nonblocking assignments made to the same reg variable in a sequential always block, then the last assignment is picked up for logic synthesis.
For example
always @ (posedge clk) begin
out <= in1^in2;
out <= in1 &in2;
out <= in1|in2;
In the example just shown, it is the OR logic that is the last assignment. Hence, the logic synthesized was indeed the OR gate. Had the last assignment been the “&” operator, it would have synthesized an AND gate.
Extra Questions :-
Note : FIFO and STA Numerical Questions are not asked in Qualcomm. But basics of STA like theory related to setup and hold time may be asked.
1) Given the following FIFO and rules, how deep does the FIFO need to be to prevent underflow or overflow?
RULES:
1) frequency(clk_A) = frequency(clk_B) / 4
2) period(en_B) = period(clk_A) * 100
3) duty cycle(en_B) = 25%
Solution.
Assume clk_B = 100MHz (10ns)
From (1), clk_A = 25MHz (40ns)
From (2), period(en_B) = 40ns * 400 = 4000ns, but we only output for 1000ns,due to (3), so 3000ns of the enable we are doing no output work. Therefore, FIFO size = 3000ns/40ns = 75 entries
2) Design a circuit that calculates the square of a number? It should not use any multiplier circuits. It should use Multiplexers and other logic?
Solution.
1^2=0+1=1
2^2=1+3=4
3^2=4+5=9
4^2=9+7=16
5^2=16+9=25
See a pattern yet? To get the next square, all you have to do is add the next odd number to the previous square that you found. See how 1,3,5,7 and finally 9 are added. Wouldn’t this be a possible solution to your question since it only will use a counter, multiplexer and a couple of adders? It seems it would take n clock cycles to calculate square of n.
3) What is difference between RAM and FIFO?
Solution.
FIFO does not have address lines. Ram is used for storage purpose where as FIFO is used for synchronization purpose i.e. when two peripherals are working in different clock domains then we will go for FIFO.
4) What are multi-cycle paths?
Solution.
Multi-cycle paths are paths between registers that take more than one clock cycle to become stable. For ex. analyzing the design shown in fig below shows that the output SIN/COS requires 4 clock-cycles after the input ANGLE is latched in. This means that the combinatorial block (the Unrolled Cordic) can take up to 4 clock periods (25MHz) to propagate its result. Place and Route tools are capable of fixing multi-cycle paths problem.
5) What is false path? How it determine in ckt? What the effect of false path in ckt?
Solution.
By timing all the paths in the circuit the timing analyzer can determine all the critical paths in the circuit. However, the circuit may have false paths, which are the paths in the circuit which are never exercised during normal circuit operation for any set of inputs.
An example of a false path is shown in figure below.
STA (Static Timing Analysis) tools are able to identify simple false paths; however they are not able to identify all the false paths and sometimes report false paths as critical paths. Removal of false paths makes circuit testable and its timing performance predictable (sometimes faster)
6) What is slack?
Solution.
'Slack' is the amount of time you have that is measured from when an event 'actually happens' and when it 'must happen. The term 'actually happens' can also be taken as being a predicted time for when the event will 'actually happen'. When something 'must happen' can also be called a 'deadline' so another definition of slack would be the time from when
something 'actually happens' (call this Tact) until the deadline (call this Tdead).
Slack = Tdead - Tact.
Negative slack implies that the 'actually happen' time is later than the 'deadline' time...in other words it's too late and a timing violation....you have a timing problem that needs some attention.
7) What is skew, what are problems associated with it and how to minimize it?
Solution.
In circuit design, clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times.
This is typically due to two causes. The first is a material flaw, which causes a signal to travel faster or slower than expected. The second is distance: if the signal has to travel the entire length of a circuit, it will likely (depending on the circuit's size) arrive at different parts of the circuit at different times. Clock skew can cause harm in two ways. Suppose that a logic path travels through combinational logic from a source flip-flop to a destination flip-flop. If the destination flip-flop receives the clock tick later than the source flip-flop, and if the logic path delay is short enough, then the data signal might arrive at the destination flip-flop before the clock tick, destroying there the previous data that should have been clocked through. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through. If the destination flip-flop receives the clock tick earlier than the source flip-flop, then the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period.
Clock skew, if done right, can also benefit a circuit. It can be intentionally introduced to decrease the clock period at which the circuit will operate correctly, and/or to increase the setup or hold safety margins. The optimal set of clock delays is determined by a linear program, in which a setup and a hold constraint appear for each logic path. In this linear program, zero clocks skew is merely a feasible point. Clock skew can be minimized by proper routing of clock signal (clock distribution tree) or putting variable delay buffer so that all clock inputs arrive at the same time.
8) For the Circuit Shown below, what is the Maximum Frequency of Operation? Are there any hold time violations for FF2? If yes, how do you modify the circuit to avoid them?
Solution.
The minimum time period = 3+2+(1+1+1) = 8ns
Maximum Frequency = 1/8n= 125MHz.
And there is a hold time violation in the circuit, because of feedback, if you observe, tcq2+AND gate delay is less than thold2,To avoid this we need to use even number of inverters(buffers). Here we need to use 2 inverters each with a delay of 1ns. Then the hold time value exactly meets.
9) What are the different ways synchronize between two clock domains?
Solution.
The following section explains clock domain interfacing. One of the biggest challenges of system-on-chip (SOC) designs is that different blocks operate on independent clocks.
Integrating these blocks via the processor bus, memory ports, peripheral busses, and other interfaces can be troublesome because unpredictable behavior can result when the asynchronous interfaces are not properly synchronized A very common and robust method for synchronizing multiple data signals is a handshake technique as shown in diagram below This is popular because the handshake technique can easily manage changes in clock frequencies, while minimizing latency at the crossing. However, handshake logic is significantly more complex than standard synchronization structures.
http://www.asic-world.com/tidbits/clock_domain.html
FSM1 (Transmitter) asserts the req (request) signal, asking the receiver to accept the data on the data bus. FSM2 (Receiver) generally a slow module asserts the ack (acknowledge) signal, signifying that it has accepted the data. it has loop holes: when system Receiver samples the systems Transmitter req line and Transmitter samples system Receiver ack line, they have done it with respect to their internal clock, so there will be setup and hold time violation. To avoid this we go for double or triple stage synchronizers, which increase the MTBF and thus are immune to metastability to a good extent. The figure below shows how this is done.
10) What is FIFO? How to Calculate the Depth of FIFO?
Solution.
One of the most common questions in interviews is how to calculate the depth of a FIFO. FIFO is used as buffering element or queuing element in the system, which is by common sense, is required only when you slow at reading than the write operation. So size of the FIFO basically implies the amount of data required to buffer, which depends upon data rate at which data is written and the data rate at which data is read. Statistically, Data rate varies in the system majorly depending upon the load in the system. So to obtain safer FIFO size we need to consider the worst case scenario for the data transfer across the FIFO under consideration. For worst case scenario, Difference between the data rate between write and read should be maximum. Hence, for write operation maximum data rate should be considered and for read operation minimum data rate should be considered. So in the question itself, data rate of read operation is specified by the number of idle cycles and for write operation, maximum data rate should be considered with no idle cycle.
So for write operation, we need to know Data rate = Number of data * rate of clock.
Writing side is the source and reading side becomes sinking, data rate of reading side depends upon the writing side data rate and its own reading rate which is Frd/Idle_cycle_rd. In order to know the data rate of write operation, we need to know Number of data in a Burst which we have assumed to be B.So following up with the equation as explained below:
Fifo size = Size to be buffered = B - B * Frd / (Fwr* Idle_cycle_rd _rd ).
Here we have not considered the synchronizing latency if Write and Read clocks are Asynchronous. Greater the Synchronizing latency, higher the FIFO size requirement to buffer more additional data written.
FIFO Depth Calculation:
Assume that we have to design a FIFO with following requirements and we want to calculate minimum FIFO depth
· A synchronized FIFO
· Writing clock 30MHz - F1
· Reading clock 40MHz - F2
· Writing Burst Size - B
· Case 1 : There is 1 idle clock cycle for reading side - I
· Case 2 : There is 10 idle clock cycle for reading side – I
FIFO depth calculation = B - B *F2/ (F1*I)
If we have alternate read cycles i.e. between two read cycles there is IDLE cycle.
FIFO depth calculation = B - B * F2/ (F1*2)
In our present problem FIFO depth = B - B *40/ (30*2) = B (1-2/3) =B/3
That means if our Burst amount of data is 10
FIFO DEPTH = 10/3 = 3.333 = 4 (approximately)
If B = 20 FIFO depth = 20/3 = 6.6 = 7 or 8 (Clocks are asynchronous)
If B = 30 FIFO depth = 30/3 = 10=> 10+1 = 11 (clocks are asynchronous)
If 10 IDLE cycles between two read cycles.
FIFO DEPTH = B - B *F2/ (F1*10)
= B (1-4/30)
= B * 26 /30
11) Sender sends data at the rate of 80 words/100 clocks. Receiver can consume at the rate of 8 words/10 clocks. Calculate the depth of FIFO so that no data is dropped. ( Assumptions: There is no feedback or handshake mechanism. Occurrence of data in that time period is guaranteed but exact place in those clock cycles is indeterminate.)
Solution.
Consider worst case condition:- say in first 80 clocks 80 words are given to the input but at output worst data reading rate is 8 words/10 clock i.e. in 80 clocks 64 words might have been read. So the FIFO depth required is 16. Now immediately after the 100 clock write cycle, transmitter again sends 80 words in 80 clock cycles. Here again receiver can sample only 64 data words, hence 16 words are dropping again so for a 200 clock cycle model for worst case if we need no data dropped then we require 16 + 16 = 32 deep FIFO. Hence, for 100 clock model the size is 16 and for 200 clock model the size is 32.
1------20---------------------100 101------------------181--------200
WWWWWWWWWW WWWWWWWWWW
RRRRRRRRRRRRR RRRRRRRRRRRRR
References :
1. Interview Questions => Must check-out CMOS Interview Question section from this.
2. Technical Bytes => Nice videos on STA, clock divider and general digital design concepts.
3. Digital Electronics Question Bank
4. http://www.asic-world.com/tidbits/index.html
5. Static Timing Analysis By VLSI Expert
